library IEEE;
use IEEE.std_logic_1164.all;

-- dflipflop entity
entity d_flipflop is
  port ( clk    : in  std_logic;
         D      : in  std_logic;
         Q      : out std_logic
  );
end entity d_flipflop;

--3 bit register entity
library IEEE;
use IEEE.std_logic_1164.all;

entity three_bit_register is
  port (clk       : in std_logic;
        input_l   : in std_logic;
        input_m   : in std_logic;
        input_r   : in std_logic;
        
        output_l  : out std_logic;
        output_m  : out std_logic;
        output_r  : out std_logic
      );
end entity three_bit_register;
    
--input buffer entity
library IEEE;
use IEEE.std_logic_1164.all;

entity input_buffer is
	port (	clk		: in	std_logic;

		sensor_l_in	: in	std_logic;
		sensor_m_in	: in	std_logic;
		sensor_r_in	: in	std_logic;

		sensor_l_out	: out	std_logic;
		sensor_m_out	: out	std_logic;
		sensor_r_out	: out	std_logic
	);
end entity input_buffer;

-- d flipflop architecture
architecture behavioural of d_flipflop is
begin
  process (clk)
    begin
      if (rising_edge (clk)) then
        Q <= D;
      end if;
    end process;
end architecture behavioural;

-- 3 bit register architecture  
architecture structural of three_bit_register is

component d_flipflop is
  port ( clk    : in  std_logic;
         D      : in  std_logic;
         Q      : out std_logic
  );
end component;

begin
  lbl0: d_flipflop PORT MAP (clk, input_l, output_l);
  lbl1: d_flipflop PORT MAP (clk, input_m, output_m);
  lbl2: d_flipflop PORT MAP (clk, input_r, output_r);
  
end architecture structural;

-- input buffer architecture
architecture structural of input_buffer is
  
component three_bit_register is
  port (clk       : in std_logic;
        input_l   : in std_logic;
        input_m   : in std_logic;
        input_r   : in std_logic;
        
        output_l  : out std_logic;
        output_m  : out std_logic;
        output_r  : out std_logic
      );
end component;

signal inter_l, inter_m, inter_r : std_logic;

begin
  lbl0: three_bit_register PORT MAP (clk, sensor_l_in, sensor_m_in, sensor_r_in, inter_l, inter_m, inter_r);
  lbl1: three_bit_register PORT MAP (clk, inter_l, inter_m, inter_r, sensor_l_out, sensor_m_out, sensor_r_out);
    
end architecture structural;